In recent years, in accordance with miniaturization of a semiconductor element, a method of forming a pattern having a dimension smaller than a resolution limit of lithography (threshold exposure linewidth) is required. As one of such methods, a method is known in which sidewall patterns are formed on side faces of a dummy pattern (core material) and a workpiece film is etched using the sidewall patterns as a mask. This method, for example, is disclosed in JP-A-2006-303022.
According to the conventional method disclosed in JP-A-2006-303022, etc., after forming the sidewall patterns, the dummy pattern between the sidewall patterns is removed by wet etching treatment, thereby forming a microscopic mask composed of the sidewall patterns. Recently, further miniaturization of a pattern dimension and further improvement of dimensional precision have been required to such pattern forming methods using the sidewall patterns.
However, according to the conventional method disclosed in JP-A-2006-303022, etc., accuracy of the mask pattern may be deteriorated by the inclination of the sidewall pattern due to surface tension acting in chemical solution used for removing the dummy pattern or a stress generated in the sidewall pattern or the dummy pattern, etc.